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Silicon Valley Test Workshop will be held on

October 29, 2013 in Santa Clara, CA

--- Website Update in Progress ---

From last year's Workshop: Silicon Valley 2012 Test Workshop

At last year's SVTW we had an outstanding presentation from Mathieu Duprez of MuTest Systems detailing their modular ATE approach to testing high speed memory controller interfaces such as DDR3. Their conclusion is that it is much less expensive to design and deploy a dedicated FPGA based modular system with improved accuracy and higher throughput than a Source Synchronous Tester. Reducing the cost of test is the Holy Grail and Final Test is the crucible for and PXI Modular Systems and Software Defined Instruments. Our workshop will have several PXI ATE vendors presenting on the use of these standard busses in new architectures for RF Test and mixed signal SOC Test systems to increase flexibility and drive down the Cost of Test. We'll also have presentations on new Handling Technology for 3D and Stacked Die devices plus new Wafer Probing and Test Socket advances.

Silicon Valley Test Workshop is pleased to announce Larry Desjardin as the Keynote Speaker.

Larry Desjardin is the founder and president of Modular Methods LLC, a consulting company focused on the rapidly growing modular instrument industry. He will present: The Coming Modular Disruption. More than just a trend, modular instruments are causing a disruptive shift in the test and measurement market.

Larry Desjardin

Larry Desjardin is the founder and president of Modular Methods LLC, a consulting company focused on the rapidly growing modular instrument industry. Larry joined Hewlett Packard (now Agilent Technologies), serving in several R&D and executive management positions. As an R&D Manager, Larry received the John Fluke Sr. Memorial Award in recognition of his contribution to the creation of the VXIbus. Most recently, he was General Manager of Agilent’s Modular Product Operation before retiring in 2011. Larry holds a BS Engineering from CalTech, and an MS Electrical Engineering from Stanford University. Larry also writes a regular column “Outside the Box” for Test and Measurement World./p>

Tutorial

Phil Warwick and his team will present , "Signal and Power Integrity Considerations for High Speed Digital IC Test".

From 1996 through 2007 Evaluation and Product Engineering, Inc., offered a five day course in signal integrity for Digital IC Test engineers. More than 400 test engineers attended the course in multiple countries. While much of the information presented in that course remains relevant, industry progression requires an update, especially as data rates exceed 28Gb/s. This short course, provided by R&D Circuits, Inc. in association with The Silicon Valley Test Workshop, attempts to provide that update.

For information and an outline of the Tutorial, please Click here for the pdf or Click here for a MS Word document.